1. Field of the Invention
The present invention relates to a variable frequency-dividing circuit, which comprises integrated semiconductor circuits, and can change the frequency-dividing ratio. More specifically, the present invention pertains to a variable frequency-dividing circuit operable at a high speed with low current consumption.
2. Description of the Related Art
FIG. 5 illustrates a conventional variable frequency-dividing circuit, which comprises multiple flip-flop circuits. These flip-flop circuits etch include metal Schottky field-effect transistors using GaAs (gallium/arsenic), for example. The variable frequency-dividing circuit is designed to be capable of frequency-dividing a clock signal by eight or nine.
In FIG. 5, master-slave type D flip-flop circuits 41 to 43 each output a pair of complimentary input signals with a delay of one clock. The D flip-flop circuit 41 has its output terminals Q1 and /Q1 connected to the input terminals D2 and /D2 of the D flip-flop circuit 42, respectively. The D flip-flop circuit 42 has its output terminals Q2 and /Q2 connected respectively to input terminals D3 and /D3 of the D flip-flop circuit 43. The D flip-flop circuits 41 to 43 receive a pair of complementary clock signals, CK and /CK. The output terminal Q2 of the D flip-flop circuit 42 and the output terminal Q3 of the D flip-flop circuit 43 are connected respectively through feedback wirings W1 and W2 to the input terminals of an OR gate 45. The output terminal of the OR gate 45 is connected to the input terminal /D1 of the D flip-flop circuit 41.
The output terminal /Q1 of the flip-flop circuit 41 is connected to the clock-signal input terminal CK of an edge-trigger type flip-flop circuit 44. The edge-trigger type flip-flop circuit 44 frequency-divides a signal to be output from the D flip-flop circuit 41. This flip-flop circuit 44 has its output terminal Q4 connected to an output terminal OUT and also to one of the input terminals of a NAND circuit 46. A switching control signal A for switching the frequency-dividing period is sent to the other input terminal of the NAND circuit 46. The D flip-flop circuit 43 has its reset-signal input terminal R connected to the later output terminal of the NAND circuit 46.
FIG. 6 shows the D flip-flop circuits 41 and 42. The flip-flop circuits 41 and 42 each include a master stage MS and a slave stage SL. The master stage MS has four two-input NOR gates G51 to G54, input terminals 51 and 52 where complimentary input data D and D are to be sent, and an input terminal where the clock signal CK is to be sent The slave stage SL has four two-input NOR gates G55 to G58, an input terminal 54 for the clock signal /CK, and output terminals 55 and 56 from which complimentary output data Q and /Q are to be sent.
The D flip-flop circuit 43 has a three-input NOR gate instead of the two-input NOR gate 57 in the slave stage SL as shown in FIG. 6. One input terminal of the three-input NOR gate is a reset input terminal R. When a "1"-level signal is supplied to the reset input terminal R, stored data is cleared and the output data Q is always set to "0".
FIG. 7 illustrates the edge-trigger type flip-flop circuit 44. The edge-trigger type flip-flop circuit 44 includes four two-input NOR gates G61 to G64, two three-input NOR gates G65 and G66, an input terminal 61 for the clock signal CK, and output terminals 62 and 63 for outputting complimentary signals, all connected as illustrated.
FIG. 8 shows the circuit arrangement of the two-input NOR gates G51 to G58 and G61 to G64. A depression type transistor QD1 as a load has a current path whose one end is connected to a supply potential V.sub.cc, with the other end and the gate of the transistor connected to an output terminal OP. Between the output terminal OP and the ground potential V.sub.ss is connected enhancement type switching transistors QE1 and QE2 whose current paths are connected in parallel to each other. A logical input IN1 is supplied to the gate of the transistor QE1, while a logical input IN2 is sent to the gate of the transistor QE2.
The three-input NOR gates G65 and G66 each have an additional enhancement transistor QE3 connected in parallel to the transistors QE1 and QE2 shown in FIG. 8, as indicated by the broken lines in the same diagram. A logical input IN3 is supplied to the gate of the transistor QE3.
The operation of the variable frequency-dividing circuit in FIG. 5 will now be described referring to time charts in FIGS. 9 and 10.
First, the case of frequency-dividing a clock signal by eight will be explained referring to FIG. 9.
When the switching control signal A for changing the frequency-dividing ratio has a value of "0", a signal "1" is always input to the reset input terminal R, and accordingly a signal "0" is always output from the output terminal Q3 of the D flip-flop circuit 43. At this time, the D flip-flop circuit 43 does not work, while the D flip-flop circuits 41 and 42, and the edge-trigger type flip-flop circuit 44 operate. The D flip-flop circuit 41 and 42 are synchronously driven in response to the clock signals CK and /CK, with the output terminal Q2 o the D flip-flop circuit 42 connected to the input terminal /D1 of the D flip-flop circuit 41. These flip-flop circuits 41 and 42 therefore frequency-divide the clock signals by four. The frequency-divided signal is sent from the output terminal /Q1 of the D flip-flop circuit 41, and is frequency-divided by eight by the edge-trigger flip-flop circuit 44. The resultant frequency-divided signal is then output from the flip-flop circuit 44.
Second, the case of frequency-dividing the clock signal by nine will be explained referring to FIG. 10. When the switching control signal A has a level of "1", a signal from the output terminal Q4 of the edge-trigger flip-flop circuit 44 is inverted by the NAND circuit 46, and the inverted signal is sent to the reset input terminal R. When a signal "0" is output from the output terminal Q4 of the flip-flop circuit 44, a signal "1" is sent to the reset input terminal R, and the clock signal is to be frequency-divided by eight in the same manner as described above.
When the output signal from the output terminal Q4 of the edge-trigger type flip-flop circuit 44 has a level of "1", the signal "0" is sent to the reset input terminal R to operate the D flip-flop circuit 43. Since the flip-flop circuit 43 has its output terminal Q3 connected to the input terminal /D1 of the D flip-flop circuit 41 through the OR gates 45, the D flip-flop circuits 41 and 42 frequency-divide the clock signal by four and five, alternately. As a result, the edge-trigger type flip-flop circuit 44 outputs a signal frequency-divided by nine.
The operation speed of the variable frequency-dividing circuit is defined by the operation speed of the D flip-flop circuits 41 through 43, the capacitors of the wiring W1 and W2, and a delay in operation along the route from the D flip-flop circuit 41, to the edge-trigger flip-flop circuit 44, to the NAND gate 46 and to the D flip-flop circuit 43.
Particularly when the clock signal is frequency-divided by an odd number, the signal has to pass more gate circuits than when the signal is frequency-divided by an even number, so that the operation speed gets slower. Moreover, in general, the field-effect transistor is less capable of driving a current than a bipolar transistor. Since the above-described variable frequency-dividing circuit comprises the field-effect transistors, its operation speed drops further.
As a solution to this shortcoming, the current-driving performance of each gate may be improved. In this case, however, power consumption will undesirably rise in the variable frequency-dividing circuit.